Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60195 )
Change subject: intel/common/block/cse: Move EOP early in boot sequence ......................................................................
intel/common/block/cse: Move EOP early in boot sequence
Earlier while trying to optimize boot time EOP time kept increasing when boot time reduced.This was because CSE was busy. When EOP was moved later in boot stage it again created issue since CSE was busy with loading other payload, it delayed response to EOP command.
In order to meet timing requirement, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible.This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message.
Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board.
Also removing commands to set CSE active/idle state since now EOP is being sent before HECI disable.
BUG=b:211085685 BRANCH=None TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time.
Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 8 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60195/1
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 4e1c563..321f918 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -196,26 +196,19 @@ return; }
- set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
timestamp_add_now(TS_ME_BEFORE_END_OF_POST); handle_cse_eop_result(cse_send_eop()); timestamp_add_now(TS_ME_AFTER_END_OF_POST); - - set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); }
/* - * Ideally, to give coreboot maximum flexibility, sending EOP would be done as - * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must - * be performed before the HECI bus is disabled, so these boards use - * BS_PAYLOAD_LOAD, which happens before the HECI_DISABLE_USING_SMM Kconfig takes - * effect (EOP is sent using the HECI bus). - * Otherwise, EOP can be pushed a little later, and can be performed in - * BS_PAYLOAD_BOOT instead. + * Earlier when coreboot used to send EOP at late as possible caused issue + * of delayed response from CSE since CSE was busy loading other payloads. + * To resolve the issue, EOP should be sent early in the boot sequence at + * BS_DEV_INIT or BS_DEV_ENABLE. + * Sending it early meets timing requirement where CSE has not started + * loading payload and serves EOP first. + * This method reduces time to send EOP from ~60 ms to ~20 ms. */ -#if !CONFIG(HECI_DISABLE_USING_SMM) -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); -#else -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); -#endif +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, set_cse_end_of_post, NULL);