[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: replace dt option by MSR write for disabling HWP ca...

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46459 )

Change subject: mb/google/dedede: replace dt option by MSR write for disabling HWP capability
......................................................................

Patch Set 3:
> Patch Set 3:
> > Patch Set 2:
> >
> > Karthikeyan, can you tell us more about the reasons to disable ISST in "early silicon" on these boards, please?
>
> Sorry for the delay in the response. In the early revisions of Jasperlake silicon with ISST enabled, CPU hangs while booting to OS. The hang point is different - sometimes as soon as the control hits the kernel, whereas sometimes 10s after starting the kernel.
>
> Having said that, boards with those silicon revisions were used only for development purposes and have been phased out. So this support can be dropped.

Thanks for your feedback! That makes it a little easier :-)