[coreboot-gerrit] Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )

Change subject: [WIP] mainboard: Add Acer ES1-572
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Patch Set 3:

(1 comment)

This change is ready for review.

https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG@31 
PS3, Line 31: UART 2
The FSP has a UPD to enable these. Try using:

register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
    	[PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
    	[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
    	[PchSerialIoIndexUart0] = PchSerialIoDisabled,
    	[PchSerialIoIndexUart1] = PchSerialIoDisabled,
    	[PchSerialIoIndexUart2] = PchSerialIoPci,
    }"