Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... File src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex:
https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... PS13, Line 21: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF i'm curious - why 0xff here instead of 0x00?