Scott Duplichan (scott@notabs.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8394
-gerrit
commit f379482f9b1d02f5f6fdf2e6b258b7fc43acf0a9 Author: Scott Duplichan scott@notabs.org Date: Sat Feb 7 22:52:24 2015 -0600
southbridge/amd/rs780: Remove requirement for CF8/CFC config access
The AMD RS780 early initialization code originally used the CF8/CFC I/O method for PCI configuration space access. After the default configuration access method was changed to MMIO (http://review.coreboot.org/#q,aad07472), booting would hang at "PCI: pci_scan_bus for bus 01". Fix the problem by changing function rs780_nb_gfx_dev_table() so that it no longer borrows the BAR3 address needed for PCIe MMIO config usage.
Test: Build amd/mahogany_fam10 and boot on ECS A780GM-M3. Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7 Signed-off-by: Scott Duplichan scott@notabs.org --- src/southbridge/amd/rs780/rs780.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index dc5b9e4..5756cea 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -190,21 +190,10 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) { /* NB_InitGFXStraps */ u32 MMIOBase, apc04, apc18, apc24, romstrap2; - msr_t pcie_mmio_save = { 0, 0 }; volatile u32 * strap;
- // disable processor pcie mmio, if enabled - if (is_family10h()) { - msr_t temp; - pcie_mmio_save = temp = rdmsr (0xc0010058); - temp.lo &= ~1; - wrmsr (0xc0010058, temp); - } - - /* Get PCIe configuration space. */ - MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0; - /* Temporarily disable PCIe configuration space. */ - set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0); + // Choose a base address that is unused and routed to the RS780 + MMIOBase = 0xFFC00000;
// 1E: NB_BIF_SPARE set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7); @@ -262,13 +251,6 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) pci_write_config32(dev, 0x18, apc18); pci_write_config32(dev, 0x24, apc24);
- /* Enable PCIe configuration space. */ - set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28); - - // restore processor pcie mmio - if (is_family10h()) - wrmsr (0xc0010058, pcie_mmio_save); - printk(BIOS_INFO, "GC is accessible from now on.\n"); }