[coreboot-gerrit] Change in coreboot[master]: mainboard/google: Move memory_variant_sku() call site

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36494 )

Change subject: mainboard/google: Move memory_variant_sku() call site
......................................................................

mainboard/google: Move memory_variant_sku() call site

Move the call site down to be local to where it is needed.
This makes it easier to split the function into two variants,
one for handling the SPD data sourced from CBFS or from SMBus.

BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I4b04fe392539e799f491ffc77d8a79a42724f052
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/romstage.c
1 file changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36494/1

diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
index 50d9066..07864e6 100644
--- a/src/mainboard/google/hatch/romstage.c
+++ b/src/mainboard/google/hatch/romstage.c
@@ -32,11 +32,9 @@
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
    struct cnl_mb_cfg memcfg;
-	int mem_sku;
    int is_single_ch_mem;

variant_memory_params(&memcfg);
-	mem_sku = variant_memory_sku();
    /*
     * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
     * channel skus and 0 for dual channel skus.
@@ -48,6 +46,7 @@
     * Dual-DIMM memory is not used in hatch family, so we only
     * fill in spd_info for CH0D0 and CH1D0 here.
     */
+	int mem_sku = variant_memory_sku();
    memcfg.spd[0].read_type = READ_SPD_CBFS;
    memcfg.spd[0].spd_spec.spd_index = mem_sku;
    if (!is_single_ch_mem) {