[coreboot-gerrit] Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses

[Jes Klinke (Code Review)]

Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )

Change subject: mainboard/google/volteer: Enable long cr50 ready pulses
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Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44359/10/src/mainboard/google/volte... 
File src/mainboard/google/volteer/mainboard.c:

https://review.coreboot.org/c/coreboot/+/44359/10/src/mainboard/google/volte... 
PS10, Line 37: 		cfg->LpmStateDisableMask = LPM_S0i3_4;
> Ideally if u have implemented long TPM IRQ width then you can keep those GPIO advance PM configurati […]

This piece of code deals with the case where the external cr50 chip is not able to emit 100us pulses, and will emit 4us pulses instead, until it is upgraded.

I take what you are saying to mean that setting bit 7 of the LPM control register to zero, thereby preventing the SoC from entering S0i3.4, is not enough to guarantee that the Tiger Lake SoC will recognize a 4us pulse on a GPIO line configured to interrupt on edge.  And that additionally, I need to set override_pm=1 and make bit4:0 in gpio_pm all zero.