[coreboot-gerrit] [M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm

[Werner Zeh (Code Review)]

Attention is currently required from: Stefan Ott, Angel Pons, Arthur Heymans, Alexander Couzens.

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69297 )

Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
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Patch Set 18: Code-Review+1

(2 comments)

File src/northbridge/intel/gm45/northbridge.c:

https://review.coreboot.org/c/coreboot/+/69297/comment/7ab44db5_5290f895 
PS18, Line 264: __pci_0_00_0
Shall this better be 'pcidev_on_root(0, 0);'?

File src/southbridge/intel/i82801ix/lpc.c:

https://review.coreboot.org/c/coreboot/+/69297/comment/f2f52bb4_99b44bb3 
PS18, Line 143: __pci_0_1f_0
pcidev_on_root(0x1f, 0)?