[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39625 )

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39625/2/src/soc/intel/xeon_sp/bootb... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/39625/2/src/soc/intel/xeon_sp/bootb... 
PS2, Line 34: 		.CodeRegionLength = (UINT32)CONFIG_BIOS_REGION_SIZE,
> Do you mean like this? […]

sounds like CACHE_ROM_SIZE will do the trick here. We can drop the mainboard patch then