26 Nov
2022
26 Nov
'22
8:44 p.m.
Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Krishna P Bhat D, Tarun Tuli, Jamie Ryu, Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Usha P, Raj Astekar.
Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 )
Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
Supporting multiple SPD/Memory config is WIP. […]
The current CL is split to DDR5(CB:66190) and LP5(CB:69741) changes.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Gerrit-Change-Number: 66190
Gerrit-PatchSet: 2
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