Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48356 )
Change subject: azalia: Use `azalia_exit_reset` function ......................................................................
azalia: Use `azalia_exit_reset` function
Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/device/azalia_device.c M src/soc/intel/common/hda_verb.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/lynxpoint/hda_verb.c 8 files changed, 10 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 9306e2a..5e9c6c9 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -51,8 +51,7 @@ u32 reg32; int count;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* clear STATESTS bits (BAR + 0xe)[2:0] */ @@ -77,8 +76,7 @@ if (azalia_set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index e812ec5..ecf5a51 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -12,7 +12,7 @@ u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ @@ -28,7 +28,7 @@ goto no_codec;
/* Turn on the link and poll RESET# bit until it reads back as 1 */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index fd08528..eab8e79 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -18,8 +18,7 @@ { u8 reg8;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 31ff159..d1d3731 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -19,8 +19,7 @@ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 2d8e6d4..558f9cd 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -19,8 +19,7 @@ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 3ac0a4a..bea2e90 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -19,8 +19,7 @@ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 2510996..1224792 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -14,8 +14,7 @@ { u8 reg8;
- /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Write back the value once reset bit is set. */ diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 9caffed..f7eddf4 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -13,7 +13,7 @@ u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_exit_reset(base) < 0) goto no_codec;
/* Write back the value once reset bit is set. */