[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add a workaround for cnvi

[Jamie Chen (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Karthik Ramasubramanian.
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 )

Change subject: soc/intel/jasperlake: Add a workaround for cnvi
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Patch Set 3:

(3 comments)

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63675/comment/8b91f5d5_9a477564 
PS1, Line 424: 	/*
             : 	 * This is a workaround to mitigate higher SoC power consumption in S0ix
             : 	 * when the CNVI has background activity.
             : 	 *
             : 	 * This setting can only be enabled if xtalsdqdis (Bit 22) in cppmvric1
             : 	 * register is 1.
             : 	 * 1: Enabled ; 0: Disabled
             : 	 */
             : 	bool cnvi_s0ix_wa;
> Can we also please mention […]

Done

File src/soc/intel/jasperlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/63675/comment/5e51a888_f7539b54 
PS2, Line 66: write32
> setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS);

Done

https://review.coreboot.org/c/coreboot/+/63675/comment/cd7c9902_0e4c14e9 
PS2, Line 70: write32
> clearbits32

Done