[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Determine PCIe RP enable mask using device on/of...

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )

Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... 
File src/soc/intel/alderlake/pcie_rp.c:

https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... 
PS2, Line 18: /* TODO check how to determine CPU PCIE port */
> From ADL EDS, need to check 01.0, 06.0 and 06.2... need to work out how to deal with it here.

We need to understand how each logical PCI device maps to the CpuPcieRpEnable UPD, the help text isn't helpful:
```
  Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
  for port1, bit1 for port2, and so on.
```

I'd guess it's gen5 port is bit 0, gen 4 port 1 is bit 1, gen 4 port 2 is bit 2, but IDK