[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Subrata Banik (Code Review)]

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 21: Code-Review+2

(1 comment)

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85454/comment/a9bb8a97_02cd1abc?usp... :
PS21, Line 387: 	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> Would https://review.coreboot.org/c/coreboot/+/86532 be acceptable ?

I'm planning to take step approach here by implementing https://review.coreboot.org/c/coreboot/+/86509/1 and then move the SoC UX into basecode. Now we would have two kinds of UX implementation (for ADL using libgfxinit and MTL onwards using uGOP).

Note, we need some special handling like https://review.coreboot.org/c/coreboot/+/86509/1/src/soc/intel/pantherlake/r... to avoid overlapping text message due to low-battery w/ MRC update in pipeline

At this moment, I would prefer to land the SoC changes as is and take the refactoring with upcoming CLs. let me you @julius has any concerns