Hello Subrata Banik, Aamir Bohra, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37865
to look at the new patch set (#4).
Change subject: mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0 ......................................................................
mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0
With PchPmSlpS0Vm075VSupport FSP UPD set, SoC requires gpio clk to be power gated, but when gpio clk is power gated, it requires longer interrupt assertion from device.
This change fixes runtime s0ix with PchPmSlpS0Vm075VSupport set.
And it sets gpio clk power gating settings in SPIO PS0/PS3 so that cr50 doesn't need longer interrupt assertion.
BUG=:141831197 TEST=run suspend/stress, cold reset tests 2500 cycles and check no irq missed in kernel msg
Change-Id: I33a3d5897ec40afee29759160963363c322d5ad0 Signed-off-by: Kane Chen kane.chen@intel.com --- M src/mainboard/google/hatch/mainboard.asl 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37865/4