Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )
Change subject: soc/intel/ptl: Add GPE1 defines ......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84297/comment/d1b5d4d2_353fdb17?usp... : PS9, Line 12: STD
standard?
STD GPE have been used for Intel's GPE bits in this case. I can add more here.
https://review.coreboot.org/c/coreboot/+/84297/comment/d8fc487f_b2bcf7dd?usp... : PS9, Line 12: NOTE: All GEP1 bits are STD GPE bits.
Shouldn’t this then go into some common directory?
GPE1 implementation is SOC specific.
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/071e11d8_5fdafe04?usp... : PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
Subrata, we are still switching in between using GPE0 and GPE1 for further validation until we ver […]
Subrata, if these 3 defines are here, we won't be using the defines in ./soc/intel/common/block/include/intelblocks/pmclib.h
#if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) #define GPE1_STS(x) (0x0 + ((x) * 4)) #define GPE1_EN(x) (0x0 + ((x) * 4)) #define GPE1_REG_MAX 0 #endif
and ending up we will add GEP1 blocks in FADT.