Attention is currently required from: Jason Glenesk, Fred Reitberger.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69411 )
Change subject: mb/amd/birman/gpio: Configure birman GPIOs ......................................................................
Patch Set 2:
(6 comments)
File src/mainboard/amd/birman/gpio.c:
https://review.coreboot.org/c/coreboot/+/69411/comment/af40ac72_7de59a9e PS2, Line 19: PAD_GPI(GPIO_3, PULL_UP), this should probably be PAD_SCI instead of PAD_GPI
https://review.coreboot.org/c/coreboot/+/69411/comment/02e037ce_da7497cc PS2, Line 31: PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), i'm not 100% sure what this does and if it needs the SCI, but since it's a GEVENT capable pin, i'd guess that this is correct
https://review.coreboot.org/c/coreboot/+/69411/comment/41aaab8d_6f978b61 PS2, Line 33: PAD_GPO(GPIO_10, HIGH), have you checked this with the reference implementation? not sure what's the correct default here
https://review.coreboot.org/c/coreboot/+/69411/comment/9a606bb1_f7f64f06 PS2, Line 37: PAD_GPO(GPIO_12, HIGH), not sure what this one does and if this is the correct output level. have you checked with the reference implementation?
https://review.coreboot.org/c/coreboot/+/69411/comment/5507d8ca_338d8b1e PS2, Line 80: PAD_GPO(GPIO_42, HIGH), have you checked this with the reference implementation? not sure what's the correct default here
https://review.coreboot.org/c/coreboot/+/69411/comment/46cf4727_000ebda4 PS2, Line 91: /* SPI1_CS1_L */ : PAD_NF(GPIO_74, SPI1_CS1_L, PULL_NONE), this is used as GPO and not as SPI1 #CS1