Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 556: pci_s_deassert_secondary_reset(p2peg);
Petr, can you experiment with mdelay(25) in between with kontron/986m-lcd and add-on graphics?
Conventional PCI had Trst 1 ms minimum for RST# asserted and Trhfa 1 second when add-on hardware must be ready.
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 591: printk(BIOS_DEBUG, "PCIe link training ..."); This deserves a rewrite, lines 615-625 repeat 591-601. I think the loop below is the PCIe retry mechanism that somewhat replaced Trhfa delay in PCIe specs.