[coreboot-gerrit] Change in ...coreboot[master]: cpu/intel/common: Extend FSB detection to cover TSC

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31340

Change subject: cpu/intel/common: Extend FSB detection to cover TSC
......................................................................

cpu/intel/common: Extend FSB detection to cover TSC

Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/intel/common/fsb.c
1 file changed, 23 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31340/1

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 83220de..d06739c 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -18,14 +18,13 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>

-static int get_fsb(void)
+static int get_fsb_tsc(int *fsb, int *ratio)
 {
    struct cpuinfo_x86 c;
    static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
    static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
    static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
    msr_t msr;
-	int ret = -2;

get_fms(&c, cpuid_eax(1));
    switch (c.x86) {
@@ -33,49 +32,61 @@
    	switch (c.x86_model) {
    	case 0xe:  /* Core Solo/Duo */
    	case 0x1c: /* Atom */
-			ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			*fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			*ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24;
    		break;
    	case 0xf:  /* Core 2 or Xeon */
    	case 0x17: /* Enhanced Core */
-			ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			*fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			*ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24;
    		break;
    	case 0x25: /* Nehalem BCLK fixed at 133MHz */
-			ret = 133;
+			*fsb = 133;
+			*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
    		break;
    	case 0x2a: /* SandyBridge BCLK fixed at 100MHz */
    	case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
    	case 0x3c: /* Haswell BCLK fixed at 100MHz */
    	case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
-			ret = 100;
+			*fsb = 100;
+			*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
    		break;
    	}
    	break;
    case 0xf: /* Netburst */
    	msr = rdmsr(MSR_EBC_FREQUENCY_ID);
+		*ratio = msr.lo >> 24;
    	switch (c.x86_model) {
    	case 0x2:
-			ret = f2x_fsb[(msr.lo >> 16) & 7];
+			*fsb = f2x_fsb[(msr.lo >> 16) & 7];
    		break;
    	case 0x3:
    	case 0x4:
    	case 0x6:
-			ret = core2_fsb[(msr.lo >> 16) & 7];
+			*fsb = core2_fsb[(msr.lo >> 16) & 7];
    		break;
    	}
+	default:
+		return -2;
    }
-	return ret;
+	if (*fsb > 0)
+		return 0;
+	return -1;
 }

int get_ia32_fsb(void)
 {
-	int ret;
+	int ret, fsb, ratio;

-	ret = get_fsb();
+	ret = get_fsb_tsc(&fsb, &ratio);
    if (ret == -1)
    	printk(BIOS_ERR, "FSB not found\n");
    if (ret == -2)
    	printk(BIOS_ERR, "CPU not supported\n");
-	return ret;
+	if (ret < 0)
+		return ret;
+
+	return fsb;
 }

/**