Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59701 )
Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ......................................................................
soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701 Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/psp.c 5 files changed, 36 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 2aa000e..e749d75 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -5,9 +5,6 @@
#include <stdint.h>
-/* Get the mailbox base address - specific to family of device. */ -void *soc_get_mbox_address(void); - #define SMM_TRIGGER_IO 0 #define SMM_TRIGGER_MEM 1
diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 076d354..55070f2 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> #include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> #include <cbfs.h> #include <region_file.h> #include <timer.h> @@ -8,8 +12,39 @@ #include <amdblocks/psp.h> #include <soc/iomap.h> #include <soc/northbridge.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> #include "psp_def.h"
+#define PSP_MAILBOX_OFFSET 0x70 + +static void *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + /* Check for presence of the PSP */ + if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { + printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", + PSP_DEV, PSP_FUNC); + return 0; + } + + /* Determine if Bar3Hide has been set, and if hidden get the base from + * the MSR instead. */ + if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { + psp_mmio = rdmsr(PSP_ADDR_MSR).lo; + if (!psp_mmio) { + printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); + return 0; + } + } else { + psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } + + return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); +} + static u32 rd_mbox_sts(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_status); diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index e2f51d8..aef7dad 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -19,7 +19,7 @@ return psp_mmio; }
-void *soc_get_mbox_address(void) +static void *soc_get_mbox_address(void) { uintptr_t psp_mmio = soc_get_psp_base_address(); if (!psp_mmio) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 97eb806..74e9498 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -181,7 +181,6 @@ void soc_enable_psp_early(void);
#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */
#define PSP_BAR_ENABLES 0x48 #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index b001d5f..e2a74bd 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -3,8 +3,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/msr.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -30,30 +28,3 @@ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; - -void *soc_get_mbox_address(void) -{ - uintptr_t psp_mmio; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return 0; - } - - /* Determine if Bar3Hide has been set, and if hidden get the base from - * the MSR instead. */ - if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(PSP_ADDR_MSR).lo; - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); - return 0; - } - } else { - psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - } - - return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); -}