Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52114 )
Change subject: mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors ......................................................................
mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors
pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training.
BUG=b:182202136 TEST=See PCIe devices train & enumerate
Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/52114/1
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index b0f4fa9..3227812 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/platform_descriptors.h> +#include <soc/gpio.h> #include <types.h>
/* TODO: test if this really works */ @@ -14,6 +15,7 @@ .function_number = 1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, + .gpio_group_id = GPIO_29, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* SD */ @@ -25,6 +27,7 @@ .function_number = 2, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_70, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */ @@ -36,6 +39,7 @@ .function_number = 3, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, + .gpio_group_id = GPIO_18, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* NVME */ @@ -47,6 +51,7 @@ .function_number = 4, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, + .gpio_group_id = GPIO_40, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} } };