Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59000 )
Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ......................................................................
mb/google,intel: Add ChromeOS GPIOs to onboard.h
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/auron/chromeos.c A src/mainboard/google/auron/onboard.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/onboard.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/chromeos.c A src/mainboard/intel/baskingridge/onboard.h M src/mainboard/intel/emeraldlake2/chromeos.c A src/mainboard/intel/emeraldlake2/onboard.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/strago/onboard.h 18 files changed, 89 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59000/1
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 77a396b..cd1db11 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -7,8 +7,7 @@ #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h>
-/* SPI Write protect is GPIO 16 */ -#define CROS_WP_GPIO 58 +#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h new file mode 100644 index 0000000..6d4ff28 --- /dev/null +++ b/src/mainboard/google/auron/onboard.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AURON_ONBOARD_H +#define AURON_ONBOARD_H + +/* SPI Write protect is GPIO 58 */ +#define CROS_WP_GPIO 58 + +#endif diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 0b431a2..43b9e78 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -11,9 +11,8 @@ #include <ec/quanta/ene_kb3940q/ec.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" +#include "onboard.h"
-#define WP_GPIO 6 -#define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0
void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index b8da862..2e780c9 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -16,4 +16,10 @@
/* 0x00: White LINK LED and Amber ACTIVE LED */ #define BUTTERFLY_NIC_LED_MODE 0x00 + +/* SPI write protect, active low */ +#define WP_GPIO 6 + +#define DEVMODE_GPIO 54 + #endif diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 0bc7897..370388d 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -26,12 +26,12 @@
int get_write_protect_state(void) { - return get_gpio(57); + return get_gpio(GPIO_SPI_WP); }
static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), };
void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index 7e351e4..efcda92 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -16,4 +16,8 @@ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a #define BOARD_TOUCHSCREEN_IRQ 22
+#define GPIO_REC_MODE 9 + +#define GPIO_SPI_WP 57 + #endif diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 66bcbbf..4cabf91 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -9,9 +9,9 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <ec/compal/ene932/ec.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" + +#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios) { @@ -20,7 +20,7 @@
struct lb_gpio chromeos_gpios[] = { /* Lid switch GPIO active high (open). */ - {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {GPIO_LID, ACTIVE_HIGH, get_lid_switch(), "lid"},
/* Power Button */ {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, @@ -34,32 +34,27 @@
int get_lid_switch(void) { - return get_gpio(15); + return get_gpio(GPIO_LID); }
int get_write_protect_state(void) { - return !get_gpio(70); + return !get_gpio(GPIO_SPI_WP); }
int get_recovery_mode_switch(void) { - u8 gpio = !get_gpio(68); - /* GPIO68, active low. For Servo support - * Treat as active high and let the caller invert if needed. */ - printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio); - - return gpio; + return !get_gpio(GPIO_REC_MODE); }
static int parrot_ec_running_ro(void) { - return !get_gpio(68); + return get_recovery_mode_switch(); }
static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), };
void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index 9bece67..d564c56 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -9,4 +9,13 @@ #define BOARD_TRACKPAD_IRQ_PVT 20 #define BOARD_TRACKPAD_WAKE_GPIO 0x1c
+#define GPIO_LID 15 + +/* GPIO68, active low. For Servo support + * Treat as active high and let the caller invert if needed. */ +#define GPIO_REC_MODE 68 + + +#define GPIO_SPI_WP 70 + #endif diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a213a6d..7142940 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -19,12 +19,12 @@
int get_write_protect_state(void) { - return get_gpio(58); + return get_gpio(GPIO_SPI_WP); }
static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), };
void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 6b7fdb2..a1f30fd 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -23,4 +23,7 @@ #define PEPPY_BOARD_VERSION_PROTO 0 #define PEPPY_BOARD_VERSION_EVT 1
+/* Write protect is active high */ +#define GPIO_SPI_WP 58 + #endif diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 09e6cf2..41dd51a 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -3,15 +3,9 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> - #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" -#include <ec/quanta/it8518/ec.h>
void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,7 +29,7 @@
int get_write_protect_state(void) { - return !get_gpio(7); + return !get_gpio(GPIO_SPI_WP); }
int get_lid_switch(void) @@ -76,8 +70,7 @@
static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), };
void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index a31dffd..2f9b92d 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -11,4 +11,7 @@ #define XHCI_PREBOOT 0 // No PreOS boot support #define XHCI_STREAMS 1 // Sure, lets have streams
+/* Write protect is active low */ +#define GPIO_SPI_WP 7 + #endif diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 04300e4..555e3d5 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -12,7 +11,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
/* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -32,18 +31,18 @@ * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return get_gpio(69); + return get_gpio(GPIO_REC_MODE); }
int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(22); + return !get_gpio(GPIO_SPI_WP); }
static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), };
void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h new file mode 100644 index 0000000..66812a5 --- /dev/null +++ b/src/mainboard/intel/baskingridge/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BASKINGRIDGE_ONBOARD_H +#define BASKINGRIDGE_ONBOARD_H + +/* Recovery: GPIO69, active high - SV_DETECT - J8E3 (silkscreen: J8E2) */ +#define GPIO_REC_MODE 69 + +/* Write protect is active low */ +#define GPIO_SPI_WP 22 + +#endif diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 254ac95..192e177 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -12,7 +11,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
/* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -29,18 +28,18 @@ int get_recovery_mode_switch(void) { /* Recovery: GPIO22, active low */ - return !get_gpio(22); + return !get_gpio(GPIO_REC_MODE); }
int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(48); + return !get_gpio(GPIO_SPI_WP); }
static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), };
void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h new file mode 100644 index 0000000..658ad83 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EMERALDLAKE2_ONBOARD_H +#define EMERALDLAKE2_ONBOARD_H + +/* Recovery: GPIO22, active low */ +#define GPIO_REC_MODE 22 + +/* Write protect is active low */ +#define GPIO_SPI_WP 48 + +#endif diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 4e99684..531029d 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -6,10 +6,7 @@ #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#define WP_GPIO GP_E_22 - -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 +#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index bc2e7a2..d8af569 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -29,6 +29,9 @@ #define JACK_DETECT_GPIO_INDEX 95 /* SCI: Gpio index in N bank */ #define BOARD_SCI_GPIO_INDEX 15 + +#define WP_GPIO GP_E_22 + /* Trackpad: Gpio index in N bank */ #define BOARD_TRACKPAD_GPIO_INDEX 18