HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18553
-gerrit
commit 6ff7c1978aa01f039f3f9a1f9fb1d4d27a4e6664 Author: Elyes HAOUAS ehaouas@noos.fr Date: Fri Mar 3 12:50:22 2017 +0100
nb/intel/i945: Update comments about supported DIMMs
i945G support 4 DIMMS. SPD at 0x50, 0x51, 0x52 and 0x53
Change-Id: Ib315e640bc7b9aced4701c359e4aeff7a11a7c8d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/intel/i945/raminit.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b5cce9c..2117d16 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -318,13 +318,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) int i;
/** - * i945 supports two DIMMs, in two configurations: + * i945GM supports two DIMMs, in two configurations: * * - single channel with two DIMMs * - dual channel with one DIMM per channel * * In practice dual channel mainboards have their SPD at 0x50/0x52 * whereas single channel configurations have their SPD at 0x50/0x51. + * Note that i945GC support 4 DIMMs with SPD at 0x50/0x51/0x52/0x53. * * The capability register knows a lot about the channel configuration * but for now we stick with the information we gather via SPD. @@ -339,7 +340,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) }
/** - * Since we only support two DIMMs in total, there is a limited number + * Since we only support two DIMMs for i94GM in total, there is a limited number * of combinations. This function returns the type of DIMMs. * return value: * [0:7] lower DIMM population