[coreboot-gerrit] Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Add _HID for privacy screen device

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61125 )

Change subject: mb/google/guybrush/var/nipperkin: Add _HID for privacy screen device
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mb/google/guybrush/var/nipperkin: Add _HID for privacy screen device

BUG=b:204401306
BRANCH=guybrush
TEST=emerge-guybrush coreboot

Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/guybrush/Kconfig.name
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
2 files changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/61125/1

diff --git a/src/mainboard/google/guybrush/Kconfig.name b/src/mainboard/google/guybrush/Kconfig.name
index e8b1b32..a682c76 100644
--- a/src/mainboard/google/guybrush/Kconfig.name
+++ b/src/mainboard/google/guybrush/Kconfig.name
@@ -7,6 +7,7 @@
 config BOARD_GOOGLE_NIPPERKIN
    bool "->  Nipperkin"
    select BOARD_GOOGLE_BASEBOARD_GUYBRUSH
+	select DRIVERS_GFX_GENERIC

config BOARD_GOOGLE_DEWATT
    bool "->  Dewatt"
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index f9092a2..d849f0d 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -161,6 +161,19 @@
    }"

device domain 0 on
+		device ref gpp_gfx_bridge_0 on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				register "device[0].name" = ""LCD""
+				# Use Chrome OS privacy screen _HID
+				register "device[0].hid" = ""GOOG0010""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].addr" = "0x80010400"
+				register "device[0].privacy.enabled" = "1"
+				register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_5)"
+				device pci 00.0 on end
+			end
+		end
    	device ref gpp_bridge_2 on
    		# Required so the NVMe gets placed into D3 when entering S0i3.
    		chip drivers/pcie/rtd3/device