Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33129 )
Change subject: soc/intel/cannonlake: set temperature threshold for PCH Thermal Sensor
......................................................................
Patch Set 9: Code-Review+1
(4 comments)
Overall LGTM. Some minor nits.
https://review.coreboot.org/c/coreboot/+/33129/9/src/soc/intel/cannonlake/in...
File src/soc/intel/cannonlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/33129/9/src/soc/intel/cannonlake/in...
PS9, Line 71: #define THERMAL_BASE_ADDRESS 0xfe600000
Not used anymore.
https://review.coreboot.org/c/coreboot/+/33129/9/src/soc/intel/cannonlake/th...
File src/soc/intel/cannonlake/thermal.c:
https://review.coreboot.org/c/coreboot/+/33129/9/src/soc/intel/cannonlake/th...
PS9, Line 40:
nit:
if (!res)
return NULL;
https://review.coreboot.org/c/coreboot/+/33129/9/src/soc/intel/cannonlake/th...
PS9, Line 87: /* Use default pre-ram bar */
Comment is not true anymore.
https://review.coreboot.org/c/coreboot/+/33129/9/src/soc/intel/cannonlake/th...
PS9, Line 89: PCH
ERROR: PCH thermalbar not found!
So that it gets caught by test scripts.
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