Furquan Shaikh (furquan@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18413
-gerrit
commit ae7962a58c790df25e8aff28b97dc362101670b2 Author: Furquan Shaikh furquan@chromium.org Date: Mon Feb 20 13:33:32 2017 -0800
drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load
Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed.
BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully.
Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh furquan@chromium.org --- src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 6 ++++++ src/drivers/intel/fsp1_1/ramstage.c | 14 ++++++++++++-- src/drivers/intel/fsp2_0/include/fsp/api.h | 7 +++++++ src/drivers/intel/fsp2_0/silicon_init.c | 16 ++++++++++++---- 4 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 5ce6aa8..a9f6a8d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -21,6 +21,12 @@ #include <soc/intel/common/util.h> #include <stdint.h>
+/* + * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately + * from calling silicon init. It might be required in cases where stage cache is + * no longer available by the point SoC calls into silicon init. + */ +void fsp_load(void); /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index dd1abbe..7d9ff8e 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -185,11 +185,15 @@ static int fsp_find_and_relocate(struct prog *fsp) return 0; }
-void intel_silicon_init(void) +void fsp_load(void) { + static int load_done; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3();
+ if (load_done) + return; + if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); @@ -201,7 +205,13 @@ void intel_silicon_init(void) /* FSP_INFO_HEADER is set as the program entry. */ fsp_update_fih(prog_entry(&fsp));
- fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup); + load_done = 1; +} + +void intel_silicon_init(void) +{ + fsp_load(); + fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3()); }
/* Initialize the UPD parameters for SiliconInit */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 3b4334d..3532ad2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -42,6 +42,13 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); void fsp_temp_ram_exit(void);
+/* + * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S + * separately from calling silicon init. It might be required in cases where + * stage cache is no longer available by the point SoC calls into silicon init. + */ +void fsps_load(bool s3wake); + /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e6464aa..a57f976 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -62,7 +62,7 @@ static void do_silicon_init(struct fsp_header *hdr) } }
-void fsp_silicon_init(bool s3wake) +void fsps_load(bool s3wake) { struct fsp_header *hdr = &fsps_hdr; struct cbfsf file_desc; @@ -71,17 +71,20 @@ void fsp_silicon_init(bool s3wake) void *dest; size_t size; struct prog fsps = PROG_INIT(PROG_REFCODE, name); + static int load_done; + + if (load_done) + return;
if (s3wake && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsps); if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS) die("On resume fsps header is invalid\n"); - do_silicon_init(hdr); + load_done = 1; return; }
- if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); die("FSPS not available!\n"); @@ -116,6 +119,11 @@ void fsp_silicon_init(bool s3wake)
/* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); + load_done = 1; +}
- do_silicon_init(hdr); +void fsp_silicon_init(bool s3wake) +{ + fsps_load(s3wake); + do_silicon_init(&fsps_hdr); }