Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36255 )
Change subject: drivers/intel/fsp1_1: Fake microcode update to make FSP happy ......................................................................
Patch Set 3:
(1 comment)
Patch Set 2:
FWIW, this is actually consistently 6.5ms slower on google/cyan than without the patch
Is that an acceptable delay for not having to specify where the real microcode is in Kconfig?
https://review.coreboot.org/c/coreboot/+/36255/2/src/drivers/intel/fsp1_1/ca... File src/drivers/intel/fsp1_1/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/36255/2/src/drivers/intel/fsp1_1/ca... PS2, Line 259: fake_microcode: : fake_microcode_header_start: : .long 1 /* Header Version */ : .long 1 /* Microcode revision */ : .long 0x10232019 /* Date: Time of writing 23-10-2019 */ : .long 0x00010ff0 /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */ : .long 0 /* Checksum: not checked by FSP, so won't care */ : .long 1 /* Loader Revision */ : .long 1 /* Processor Flags */ : .long MCU_DATA_SIZE /* Data Size */ : .long MCU_TOTAL_SIZE /* Total Size */ : .space 12 /* Reserved */ : fake_microcode_header_end: : .space MCU_DATA_SIZE : fake_microcode_end:
This should probably be done in C code.
scratch that. It's hard to use sizeof to assembly.