[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: Update eDP phy setting for new eDP phy setting UPDs

[chris wang (Code Review)]

Attention is currently required from: Chris Wang.
Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/50214

to review the following change.

Change subject: mb/google/zork: Update eDP phy setting for new eDP phy setting UPDs
......................................................................

mb/google/zork: Update eDP phy setting for new eDP phy setting UPDs

Update eDP phy settings for new eDP phy setting UPDs.

BUG=b:171269338
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table

Signed-off-by: Chris Wang 
Change-Id: If457f6597d5163b2a22c79863c5e666cb8a2d9e6
---
M src/mainboard/google/zork/variants/vilboz/overridetree.cb
1 file changed, 12 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/50214/1

diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index c3afe13..240842f 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -24,7 +24,18 @@
    register "telemetry_vddcr_soc_offset" = "168"

# eDP phy tuning settings
-	register  "dp_phy_override" = "ENABLE_EDP_TUNINGSET"
+
+	register "edp_phy_override" = "ENABLE_EDP_TUNINGSET"
+
+	# bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3
+	register "edp_physel" = "0x1"
+
+	register "edp_tuningset" = "{
+		.dp_vs_pemph_level = 0x00,
+		.margin_deemph = 0x004b,
+		.deemph_6db4 = 0x0,
+		.boostadj = 0x80,
+	}"

# eDP power sequence. all pwr sequence numbers below are in uint of 4ms,
    # and "0" as default value
@@ -38,13 +49,6 @@
    register "pwrdown_bloff_to_varybloff" = "5"
    register "min_allowed_bl_level" = "0"

-	register "edp_tuningset" = "{
-		.dp_vs_pemph_level = 0x0,
-		.deemph_6db4 = 0x004b,
-		.boostadj = 0x0,
-		.margin_deemph = 0x80,
-	}"
-
    # USB OC pin mapping
    register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE"	# LTE instead of USB C1