[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: Enable LPIT inclusion in DSDT

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34175 )

Change subject: mb/google/hatch: Enable LPIT inclusion in DSDT
......................................................................

mb/google/hatch: Enable LPIT inclusion in DSDT

Include the lpit.asl file in Hatch's DSDT definition.

BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.

Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Subrata Banik 
Reviewed-by: Paul Fagerburg 
---
M src/mainboard/google/hatch/dsdt.asl
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Paul Fagerburg: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 243c627..87e98ea 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -51,6 +51,9 @@
    /* Chipset specific sleep states */
    #include <soc/intel/cannonlake/acpi/sleepstates.asl>

+        /* Low power idle table */
+        #include <soc/intel/cannonlake/acpi/lpit.asl>
+
    /* Chrome OS Embedded Controller */
    Scope (_SB.PCI0.LPCB)
    {