[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )

Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36552/2/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/romstage.h:

https://review.coreboot.org/c/coreboot/+/36552/2/src/soc/intel/tigerlake/inc... 
PS2, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd);
need consistent spacing around '*' (ctx:WxV)