[coreboot-gerrit] Change in coreboot[master]: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35781 )

Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3
......................................................................

soc/skl/vr_config: fix GT Loadline for KBL-U/GT3

According to the documentation[1], the Loadline in the unslased GT VR
domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC).

[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
    Platforms and 8th Generation Intel(R) Processor Family for U Quad
    Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
    Document Number: 334661-006

Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/vr_config.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index fc48558..de5ad2c 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -286,7 +286,7 @@
    	};

if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) {
-			loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6);
+			loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
    		loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6);
    	}