Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/26628 )
Change subject: mb/jetway: Get rid of whitespace before tab ......................................................................
mb/jetway: Get rid of whitespace before tab
Change-Id: Icc7d7fee38e41f4bfda685fd42bf504a788b440c Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/26628 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl M src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl M src/mainboard/jetway/pa78vm5/devicetree.cb M src/mainboard/jetway/pa78vm5/dsdt.asl 5 files changed, 24 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 8cb6748..669d7b4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -52,7 +52,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - uint32_t FcnData; + uint32_t FcnData; PCIe_SLOT_RESET_INFO *ResetInfo;
uint32_t GpioMmioAddr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index 2f22758..30e6fdc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -72,7 +72,7 @@ Notify(_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl index 0069aa9..47de049 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl @@ -49,7 +49,7 @@
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(_SB.SBRI, 0x13)) { - * Store(0,_SB.PWDE) + * Store(0,_SB.PWDE) *} */
diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 783e4ae..79915ac 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -40,7 +40,7 @@ device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 7b8b8c8..1b9d31c 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -239,9 +239,9 @@ PWMK, 1, PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */
Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(_SB.SBRI, 0x13)) { - * Store(0,_SB.PWDE) + * Store(0,_SB.PWDE) *} */
@@ -853,13 +853,13 @@ * used, so it could be removed. * * - * _GTS OEM Going To Sleep method + * _GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(_GTS, 1) { * DBGO("\_GTS\n") @@ -1026,7 +1026,7 @@
/* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\_GPE\_L0F\n") + * DBGO("\_GPE\_L0F\n") * } */
@@ -1049,19 +1049,19 @@
/* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\_GPE\_L13\n") + * DBGO("\_GPE\_L13\n") * } */
/* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\_GPE\_L14\n") + * DBGO("\_GPE\_L14\n") * } */
/* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\_GPE\_L15\n") + * DBGO("\_GPE\_L15\n") * } */
@@ -1073,7 +1073,7 @@
/* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\_GPE\_L17\n") + * DBGO("\_GPE\_L17\n") * } */
@@ -1090,7 +1090,7 @@
/* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\_GPE\_L19\n") + * DBGO("\_GPE\_L19\n") * } */
@@ -1121,7 +1121,7 @@
/* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\_GPE\_L1E\n") + * DBGO("\_GPE\_L1E\n") * } */
@@ -1131,7 +1131,7 @@ * } */
- } /* End Scope GPE */ + } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1520,7 +1520,7 @@ )
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@@ -1634,7 +1634,7 @@
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */