Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35018 )
Change subject: soc/amd/common/block: Create new SPI code ......................................................................
Patch Set 8:
(9 comments)
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 6: This overwrites the structure spi_flash_ops to use FCH SPI code instead of individual
will do.
Done
https://review.coreboot.org/c/coreboot/+/35018/2/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi_ctrl.c:
https://review.coreboot.org/c/coreboot/+/35018/2/src/soc/amd/common/block/sp... PS2, Line 474: reg32++; /* next range */
Nope, I'm protecting 2 adjacent regions. Range points to the start address of a region. […]
Done
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi_ctrl.c:
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 53: u32 addr;
Will do.
Done
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 93: E
Will do.
Done
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 109: (u32)
Will do.
Done
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 137: this sequence is controlled : * by the SPI chip driver.
I believe that I should just remove the section after the comma.
Done
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 214: If some specialized SPI flash controllers : * (e.g. x86) can perform both command and response together, it should : * be handled at SPI flash controller driver level
Left over from copy/paste. Will remove.
Done
https://review.coreboot.org/c/coreboot/+/35018/6/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi_flash.c:
https://review.coreboot.org/c/coreboot/+/35018/6/src/soc/amd/common/block/sp... PS6, Line 34: int fch_spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
Missed, next patch
Done
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi_flash.c:
https://review.coreboot.org/c/coreboot/+/35018/7/src/soc/amd/common/block/sp... PS7, Line 40: cmd_len--;
With an extra parenthesis, but I believe you're right. Will do.
Done