[coreboot-gerrit] Change in coreboot[master]: [TEST-ONLY]Update the memory timing table for Treeya to the 2T table....

[Peichao Li (Code Review)]

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35116 )

Change subject: [TEST-ONLY]Update the memory timing table for Treeya to the 2T table. Rename the table from Liara specific to simply specifying that it's using 2T command rate
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[TEST-ONLY]Update the memory timing table for Treeya to the 2T table.
Rename the table from Liara specific to simply specifying that it's using
2T command rate

BUG=139841929
TEST=build and do stress test

Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3
---
M src/mainboard/google/kahlee/OemCustomize.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35116/1

diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 886e14f..1b33b03 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -39,7 +39,7 @@
    PSO_END
 };
 /* Liara-specific 2T memory configuration */
-static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
+static const PSO_ENTRY DDR4_T2_MemoryConfiguration[] = {
    DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
    NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
    NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
@@ -58,9 +58,9 @@

void OemPostParams(AMD_POST_PARAMS *PostParams)
 {
-	if (CONFIG(BOARD_GOOGLE_LIARA))
+	if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA))
    	PostParams->MemConfig.PlatformMemoryConfiguration =
-			(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
+			(PSO_ENTRY *)DDR4_T2_MemoryConfiguration;
    else
    	PostParams->MemConfig.PlatformMemoryConfiguration =
    		(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;