[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8183: Init PLLs for DRAM

[Tristan Hsieh (Code Review)]

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28667

Change subject: mediatek/mt8183: Init PLLs for DRAM
......................................................................

mediatek/mt8183: Init PLLs for DRAM

Setup DRAM related PLLs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab
Signed-off-by: Tristan Shieh 
---
M src/soc/mediatek/mt8183/pll.c
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28667/1

diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index e0dd388..33a2b0a 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -280,6 +280,28 @@
    setbits_le32(pll->div_reg, PLL_PCW_CHG);
 }

+static void mem_pll_init(void)
+{
+	/* CLKSQ Enable */
+	setbits_le32(&mtk_apmixed->ap_pll_con0, 0x85);
+	udelay(100);
+
+	/* power on MPLL */
+	setbits_le32(&mtk_apmixed->mpll_pwr_con0, 0x3);
+	udelay(1);
+
+	/* turn off ISO of MPLL */
+	setbits_le32(&mtk_apmixed->mpll_pwr_con0, 0x1);
+	udelay(1);
+
+	/* Config MPLL freq */
+	setbits_le32(&mtk_apmixed->mpll_con1, 0x80000000);
+
+	/* enable MPLL */
+	setbits_le32(&mtk_apmixed->mpll_con0, 0x181);
+	udelay(20);
+}
+
 void mt_pll_init(void)
 {
    int i;
@@ -348,4 +370,6 @@

/* enable [14] dramc_pll104m_ck */
    setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+
+	mem_pll_init();
 }