[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/romstage: Do initial SoC commit till romstage

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45192 )

Change subject: soc/intel/alderlake/romstage: Do initial SoC commit till romstage
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45192/2/src/soc/intel/alderlake/rom... 
File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/45192/2/src/soc/intel/alderlake/rom... 
PS2, Line 48: 	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
            : 		if (config->PcieRpEnable[i])
            : 			mask |= (1 << i);
            : 	}
> { and } not required here

I would keep them, though: the body of the loop consists of multiple lines