Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86008?usp=email )
Change subject: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD ......................................................................
mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD
Enables onboard LEDs for power and reset button as well as flash chip indicator LED. Also enables POST code display. Both LEDs and PCD turn on when the system is powered and turn off once the payload is reached. This mimics the behavior on vendor firmware.
Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7 Signed-off-by: Jan Philipp Groß jeangrande@mailbox.org --- M src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c M src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb A src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c A src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c 4 files changed, 134 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/86008/1
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c index 1cec5c4..2025022 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c +++ b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c @@ -1,8 +1,46 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> #include <southbridge/intel/lynxpoint/pch.h>
-/* FIXME: remove this if not needed */ +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + void mainboard_config_superio(void) { + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x4e); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power on the status LEDs */ + pnp_set_logical_device(GPIO1_ENABLE_DEV); + pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1); + + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0xf0, 0x30); + pnp_write_config(GPIO1_DEV, 0xf1, 0x31); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index 74b6d5f..afa7f67 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -99,8 +99,10 @@ device pnp 2e.107 off end # GPIO9 device pnp 2e.8 off end # WDT device pnp 2e.108 on # GPIO0 - irq 0xe0 = 0xf9 # + GPIO0 direction - irq 0xe1 = 0xfd # + GPIO0 value + irq 0xe0 = 0xff # + GPIO0 direction + irq 0xe1 = 0x00 # + GPIO0 value + irq 0xf0 = 0x30 # + GPIO1 direction + irq 0xf1 = 0x31 # + GPIO1 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c new file mode 100644 index 0000000..1e62d65 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ +#include <arch/io.h> +#include <bootstate.h> +#include <device/device.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void turn_off_leds(void *unused) +{ + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0x27, 0xd0); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, turn_off_leds, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, turn_off_leds, NULL); diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c new file mode 100644 index 0000000..6736c15 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Cut off power to LEDs when system goes to sleep. + */ + if (slp_typ >= ACPI_S3) { + + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); + } +}