[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place

[Dinesh Gehlot (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik, Tarun.

Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email )

Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85111/comment/996b04aa_385d1067?usp... :
PS2, Line 443: !is_cse_boot_to_rw()) {
> > If we do warm reboot, the system will boot in `RW` first, but eventually boot to `RO` during CSE s […]

A dedicated CSE sync elog has been implemented to monitor the CSE synchronization process (CB:85217). The ESOL elog event is decoupled and will only indicate whether the SOL is displayed during CSE synchronization.