[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB

[Nikolai Vyssotski (Code Review)]

Attention is currently required from: Marshall Dawson, Nikolai Vyssotski, Matt Papageorge, Felix Held.
Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Matt Papageorge, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55237

to look at the new patch set (#4).

Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
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soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB

EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.

BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported

Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski 
---
M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
M src/soc/amd/common/fsp/pci/pci_routing_info.c
M src/vendorcode/amd/fsp/cezanne/FspGuids.h
3 files changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/55237/4