Brenton Dong (brenton.m.dong@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8408
-gerrit
commit 9f97ddf21b0060cfa833e3dee3d255c9fb8d4ee9 Author: Brenton Dong brenton.m.dong@intel.com Date: Tue Feb 10 14:02:31 2015 -0700
intel/fsp_baytrail: Add Windows 8.1 boot support for BayTrail SoCs
Added PCI Root Port IRQ Routing in new file pcie.asl needed for Windows
Added 3 more XHCI ports that are supported by Baytrail to xhci.asl
Change-Id: I1d01f9589407219f533c70fde867cb948751fb20 Signed-off-by: Brenton Dong brenton.m.dong@intel.com --- src/soc/intel/fsp_baytrail/acpi/pcie.asl | 166 +++++++++++++++++++++++ src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 5 + src/soc/intel/fsp_baytrail/acpi/xhci.asl | 3 + 3 files changed, 174 insertions(+)
diff --git a/src/soc/intel/fsp_baytrail/acpi/pcie.asl b/src/soc/intel/fsp_baytrail/acpi/pcie.asl new file mode 100755 index 0000000..df9fc4f --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/pcie.asl @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(RP1P, Package() +{ + // PCIE Port #1 Slot + Package() {0x0000FFFF, 0, _SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 1, _SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 2, _SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 3, _SB.PCI0.LPCB.LNKD, 0 }, +}) + +Name(RP1A, Package() +{ + // PCIE Port #1 Slot + Package() {0x0000FFFF, 0, 0, 16 }, + Package() {0x0000FFFF, 1, 0, 17 }, + Package() {0x0000FFFF, 2, 0, 18 }, + Package() {0x0000FFFF, 3, 0, 19 }, +}) + +Name(RP2P, Package() +{ + // PCIE Port #2 Slot + Package() {0x0000FFFF, 0, _SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 1, _SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 2, _SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 3, _SB.PCI0.LPCB.LNKA, 0 }, +}) + +Name(RP2A, Package() +{ + // PCIE Port #2 Slot + Package() {0x0000FFFF, 0, 0, 17 }, + Package() {0x0000FFFF, 1, 0, 18 }, + Package() {0x0000FFFF, 2, 0, 19 }, + Package() {0x0000FFFF, 3, 0, 16 }, +}) + +Name(RP3P, Package() +{ + // PCIE Port #3 Slot + Package() {0x0000FFFF, 0, _SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 1, _SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 2, _SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 3, _SB.PCI0.LPCB.LNKB, 0 }, +}) + +Name(RP3A, Package() +{ + // PCIE Port #3 Slot + Package() {0x0000FFFF, 0, 0, 18 }, + Package() {0x0000FFFF, 1, 0, 19 }, + Package() {0x0000FFFF, 2, 0, 16 }, + Package() {0x0000FFFF, 3, 0, 17 }, +}) + +Name(RP4P, Package() +{ + // PCIE Port #4 Slot + Package() {0x0000FFFF, 0, _SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 1, _SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 2, _SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 3, _SB.PCI0.LPCB.LNKC, 0 }, +}) + +Name(RP4A, Package() +{ + // PCIE Port #4 Slot + Package() {0x0000FFFF, 0, 0, 19 }, + Package() {0x0000FFFF, 1, 0, 16 }, + Package() {0x0000FFFF, 2, 0, 17 }, + Package() {0x0000FFFF, 3, 0, 18 }, +}) + +// +// PCIE Root Port #1 +// +Device(RP01) +{ + Name(_ADR, 0x001C0000) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP1A) + } Else { + Return (RP1P) + } + } +} + +// +// PCIE Root Port #2 +// +Device(RP02) +{ + Name(_ADR, 0x001C0001) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP2A) + } Else { + Return (RP2P) + } + } +} + +// +// PCIE Root Port #3 +// +Device(RP03) +{ + Name(_ADR, 0x001C0002) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP3A) + } Else { + Return (RP3P) + } + } +} + +// +// PCIE Root Port #4 +// +Device(RP04) +{ + Name(_ADR, 0x001C0003) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP4A) + } Else { + Return (RP4P) + } + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl old mode 100644 new mode 100755 index 3ee9ee0..f074a55 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -259,6 +259,11 @@ Device (IOSF) #include "xhci.asl" #endif
+#if INCLUDE_PCIE +// PCIE Device +#include "pcie.asl" +#endif + // IRQ routing for each PCI device #include "irqroute.asl"
diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl old mode 100644 new mode 100755 index 4d5367a..e51ecf2 --- a/src/soc/intel/fsp_baytrail/acpi/xhci.asl +++ b/src/soc/intel/fsp_baytrail/acpi/xhci.asl @@ -32,5 +32,8 @@ Device (XHCI) Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } Device (PRT4) { Name (_ADR, 4) } + Device (PRT5) { Name (_ADR, 5) } + Device (PRT6) { Name (_ADR, 6) } + Device (PRT7) { Name (_ADR, 7) } } }