[coreboot-gerrit] Change in coreboot[master]: soc/intel/tgl: Enable/Disable S0ix substates

[Shreesh Chhabbi (Code Review)]

Attention is currently required from: Furquan Shaikh.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Enable/Disable S0ix substates
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Patch Set 11:

(1 comment)

File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49766/comment/937f4409_8cd07aeb 
PS9, Line 60:  and UP4
> I don't think this is correct for UP4.

Ok. I thought that its applicable for both up3 and up4. I can make this only for up3. Is there a way to differentiate up3 from up4 in soc code? Do you have any suggestions to implement this?