Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35735 )
Change subject: [WIP] intel/skylake: Refactor IRQ assignments ......................................................................
Patch Set 1: Code-Review+1
(3 comments)
Patch Set 1:
(2 comments)
Is there some quirk with SI_PCH_DEVICE_INTERRUPT_CONFIG that would require entries where arguments device and function would not originate from same PCI BDF?
Also, I do not see fsp2_0/skylake/FspUpdVpd.h anywhere, how does this code work from chip_fsp20.c?
https://review.coreboot.org/c/coreboot/+/35735/1/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/interrupt.h:
https://review.coreboot.org/c/coreboot/+/35735/1/src/soc/intel/skylake/inclu... PS1, Line 37: line Can we add parens around these macro parameters while we'er here?
https://review.coreboot.org/c/coreboot/+/35735/1/src/soc/intel/skylake/irq.c File src/soc/intel/skylake/irq.c:
https://review.coreboot.org/c/coreboot/+/35735/1/src/soc/intel/skylake/irq.c... PS1, Line 192: sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
Who allocates target buffer?
It's used directly from the fsp-s memory.
fsp_silicon_init -> do_silicon_init -> platform_fsp_silicon_init_params_cb -> soc_irq_settings
params are embeddedin the FspsConfig object within the FSPS_UPD object.
https://review.coreboot.org/c/coreboot/+/35735/1/src/soc/intel/skylake/irq.c... PS1, Line 212: memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
Who allocates target buffer? FSP? But PCH_MAX_IRQ_CONFIG is not defined in FSP headers.
$ grep -r PxRcConfig 3rdparty/fsp/KabylakeFspBinPkg/ 3rdparty/fsp/KabylakeFspBinPkg/Include/FspsUpd.h: UINT8 PxRcConfig[8];