[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg

[Maulik V Vaghela (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak.
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52782 )

Change subject: soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg
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Patch Set 3:

(2 comments)

File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:

https://review.coreboot.org/c/coreboot/+/52782/comment/aa29133b_74334ef4 
PS3, Line 38: PAD_CFG0_NAFVWE_ENABLE
> Is this applicable to more than just ADL?

Yes Tim...It's common definition between multiple platforms...Like it's applicable for TGL also.

https://review.coreboot.org/c/coreboot/+/52782/comment/de3c5c41_5087ea3d 
PS3, Line 224: PAD_IOSSTATE(TxLASTRxE)
> Is this always required when selecting […]

I have tried to maintain same definition as PAD_CFG_NF for this. We need to set IOSTATE as 0x00 for NF and since we want to set NAF_VWE bit with Native function only, I have maintain same definition as PAD_CFG_NF and added this BIT for DW0