[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Tim Crawford, Cliff Huang, Subrata Banik, Maulik V Vaghela, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60183 )

Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
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Patch Set 4:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60183/comment/42fc428f_b8f95f4e 
PS4, Line 10:
> next line may be?

Done

https://review.coreboot.org/c/coreboot/+/60183/comment/ff952ed3_65866d86 
PS4, Line 12:
> can you please also highlight here that you have dropped unused argument from pcie_rtd3_acpi_method_ […]

Done

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/60183/comment/8eaec8fc_c08ab470 
PS4, Line 269: /* Read port number of root port that this device is attached to. */
             : 		pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN);
             : 		if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) {
             : 			printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp);
             : 			return;
             : 		}
             : 		/* Port number is 1-based, PMC IPC method expects 0-based. */
             : 		pcie_rp--;
> suggestion: can you please consider creating a static helper function that return the pch pci_rp num […]

👍