Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Tim Wawrzynczak. Hello build bot (Jenkins), Rizwan Qureshi, Sridhar Siricilla, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60195
to look at the new patch set (#2).
Change subject: intel/common/block/cse: Move EOP early in boot sequence ......................................................................
intel/common/block/cse: Move EOP early in boot sequence
Earlier while trying to optimize boot time EOP time kept increasing when boot time reduced. This was because CSE was busy. When EOP was moved later in boot stage it again created issue since CSE was busy with loading other payload, it delayed response to EOP command.
In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message.
Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board.
Also remove commands to set CSE active/idle state since now EOP is being sent before HECI disable.
BUG=b:211085685 BRANCH=None TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time.
Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 8 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60195/2