Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40968 )
Change subject: soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service
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Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40968/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/40968/6//COMMIT_MSG@11
PS6, Line 11: exit boot service
What is that in coreboot terms?
https://review.coreboot.org/c/coreboot/+/40968/6/src/soc/intel/tigerlake/chi...
File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/40968/6/src/soc/intel/tigerlake/chi...
PS6, Line 134: platform_fsp_notify_status
Why is it implemted here? Does FSP require BME to be cleared?
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