Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 189: __ one _
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 187: GPD_INPUT3VSEL 132 : #define GPD_SLP_LANB 133 : #define GPD__SLP_SUSB 134 keep them in-line with cnl, where GPD_ prefix was skipped? same for the others. This way the name matches with the pin names in schematics.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 302: #define GPP_SPI_MOSI_IO_0 227 : #define GPP_SPI_MOSI_IO_1 22 these two names are confusing, since there can't be two MOSI. Let's use SPI0_MOSI, SPI0_MISO
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 305: PI_FLASH_0_CSB 230 : #define GPP_SPI_FLASH_1_CSB SPI_CS0_B SPI_CS1_B
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309: missing: azalia, jtag, cpu, vgpio*