[coreboot-gerrit] Patch merged into coreboot/master: 2eaa0d4 intel: Correct MMIO related ACPI table settings

the following patch was just integrated into master:
commit 2eaa0d49e10e9c2314b0f61400a481447d1df892
Author: Dave Frodin 
Date:   Thu Apr 23 06:04:46 2015 -0600

intel: Correct MMIO related ACPI table settings

Several of the intel platforms define the region reserved
    for PCI memory resources in a location where it overlaps
    with the MMIO (MCFG) region.

Using the memory map from mohon_peak as an example:

0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
      1. 0000000000001000-000000000009ffff: RAM
      2. 00000000000a0000-00000000000fffff: RESERVED
      3. 0000000000100000-000000007fbcffff: RAM
      4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES
      5. 000000007fc00000-000000007fdfffff: RESERVED
      6. 00000000e0000000-00000000efffffff: RESERVED
      7. 00000000fee00000-00000000fee00fff: RESERVED
      8. 0000000100000000-000000017fffffff: RAM

The ACPI table describing the space set aside for PCI memory
      (not to be confused with the MMIO config space) is defined
      as the region from BMBOUND (the top of DRAM below 4GB) to
      a hardcoded value of 0xfebfffff. That region would overlap
      the MMIO region at 0xe0000000-0xefffffff. For rangeley
      the upper bound of the PCI memory space should be set
      to 0xe0000000 - 1.

The MCFG regions for several of the affected chipsets are:
      rangeley    0xe0000000-0xefffffff
      baytrail    0xe0000000-0xefffffff
      haswell     0xf0000000-0xf3ffffff
      sandybridge 0xf8000000-0xfbffffff

TEST = intel/mohonpeak and intel/bayleybay.

Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90
    Signed-off-by: Dave Frodin 
    Reviewed-on: http://review.coreboot.org/9972
    Reviewed-by: Marc Jones 
    Tested-by: build bot (Jenkins)

See http://review.coreboot.org/9972 for details.

-gerrit