Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59483 )
Change subject: soc/intel/alderlake: Add ADLP 4+4+2 power configurations ......................................................................
soc/intel/alderlake: Add ADLP 4+4+2 power configurations
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power related settings. Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for ADL-P 482(28W) and 442(45W).
BUG=b:193864533 TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen curtis.chen@intel.com Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c 4 files changed, 18 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 78f639c..afabcf0 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -29,6 +29,7 @@ ADL_M_282_15W_CORE, ADL_M_242_CORE, ADL_P_242_CORE, + ADL_P_442_45W_CORE, ADL_POWER_LIMITS_COUNT };
@@ -52,6 +53,7 @@ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_45W_CORE, TDP_45W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index fc73a89..60c149a 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -11,7 +11,7 @@ register "power_limits_config[ADL_P_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, - .tdp_pl4 = 140, + .tdp_pl4 = 90, }"
register "power_limits_config[ADL_P_682_28W_CORE]" = "{ @@ -48,6 +48,12 @@ .tdp_pl4 = 123, }"
+ register "power_limits_config[ADL_P_442_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 95, + .tdp_pl4 = 125, + }" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e182089..ed89d97 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -303,6 +303,7 @@ }
switch (mch_id) { + case PCI_DEVICE_ID_INTEL_ADL_P_ID_1: case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: return ICC_MAX_ID_ADL_P_3_MA; case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 99caacb..e30b14c 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -10,6 +10,8 @@
/* * VR Configurations for IA and GT domains for ADL-P SKU's. + * Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation + * for ADL-P 482(28W) and 442(45W). * * +----------------+-----------+-------+-------+---------+-------------+----------+ * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | @@ -19,7 +21,7 @@ * + +-----------+-------+-------+---------+-------------+----------+ * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ - * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | + * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 40 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ @@ -48,6 +50,7 @@ }
static const struct vr_lookup vr_config_ll[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, @@ -55,13 +58,15 @@ };
static const struct vr_lookup vr_config_icc[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_ICC(120, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(109, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(85, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, };
static const struct vr_lookup vr_config_tdc_timewindow[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -69,6 +74,7 @@ };
static const struct vr_lookup vr_config_tdc_currentlimit[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },