Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20914
Change subject: soc/intel/cannonlake: Add ramstage SystemAgent support ......................................................................
soc/intel/cannonlake: Add ramstage SystemAgent support
Revered memory resource within SA, also perform necessary routine for initialization during ramstage.
Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/systemagent.c 2 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/20914/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 537a973..37434bc 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,7 @@
ramstage-y += cbmem.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += systemagent.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c new file mode 100644 index 0000000..d006fb5 --- /dev/null +++ b/src/soc/intel/cannonlake/systemagent.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <intelblocks/systemagent.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/systemagent.h> + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Mmeory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); +} +